高速低功耗维特比译码器的设计与实现

Design and Implementation of a High-Speed and Low-Power Viterbi Decoder

提出了一种基于改进T 算法和回溯法的高速低功耗维特比 (Viterbi)译码器 该译码器采用了并行和流水结构以提高速度 ,减少了加 比 选模块中不必要的操作 ,并在回溯过程中采用了幸存路径复用的方法 ,为利用时钟关断技术降低系统功耗提供了可能 利用 0 2 5 μmCMOS工艺 ,成功地设计并实现了 (2 ,1,7)Viterbi译码器 ,其电路规模约为 5万等效门 ,芯片内核面积为 2 18mm2 ,译码速度可达 10 0MHz,而译码延迟仅为 32个时钟周期 。

A new architecture for high speed and low power Viterbi decoder is presented in this paper, which is based on a modified T algorithm and modified trace back methods A full parallel and pipeline structure is used to meet the speed requirements, the unnecessary operations in path metric computations are avoided in add compare select unit, and the already generated trace back routes are reused to reduce the number of trace back operations, which contribute to the low power by a clock gating technique By using 0.25μm CMOS process, the (2,1,7) Viterbi decoder is successfully designed and implemented. Its hardware scale is about 50,000 gates (2 input NAND is counted as a gate), the speed is up to 100MHz, the decoding delay is only 32 clock cycle, and the area is 2 18mm 2 without pads The proposed Viterbi decoder has great chance to be applied to digital communication systems that need high throughput and low power consumption such as DTV and HDTV