基于CPLD的校频二进制编码解码方法

Decoding Method of Calibration Frequency Binary System Code Based on CPLD

该文在校频二进制编码的基础上 ,提出用可编程逻辑器件解决校频二进制编码的解码电路复杂、占用空间过大的问题 ;给出引信解码计时功能框图 ,重点介绍如何使用硬件描述语言VHDL对可编程逻辑器件进行设计 ,实现校频二进制解码计时功能 ,并进行了模拟仿真 ,实现了引信电路的微型化和低功耗性能。与采用分立元件数字电路和单片机的设计相比较 。

This paper introduces the calibration frequency binary system code in detail,method is put forward to solve the problem that the circuit of decoding calibration frequency binary system code is too complex and which occupies too large space. Function diagram of decoding timing circuit for calibration frequency binary system code in fuzes is given. How to use VHDL language to designs CPLD and carry out the function of decoding calibration frequency binary system code to realize timing accurately is described.The design is emulated, and the result is good. This circuit of fuze is very small and using low power. The design is superior to using single chip microcomputer or using digital components.