基于FPGA的线性可变码位控制全数字锁相环的设计与仿真

Design and Simulation for the Digital Phase-Locked Loops with Linear Variable Bits Control Based on FPGA

线性可变码位控制全数字锁相环 (LVBC -DPLL)具有环路捕捉时间快的特点。该文介绍了以EDA技术作为开发手段的LVBC -DPLL的设计与实现 ,并分析了系统的稳态性能及仿真结果。

The digital phase-locked loops with linear variable bits control(LVBC- DPLL) have the features of fast catch in loop. This article introduces the desig n and implementation of LVBC-DPLL with EDA. Its performance of stable state and simulation results are also analyzed.