一种新型的全数字锁相环

A NEW DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP

该文提出了一种实现全数字锁相环的新方法。在基于该方法实现的全数字锁相环中,一种数字比例积分控制的设计结构取代了传统的一些数字环路滤波控制方法。通过线性近似,该文推导出该锁相环系统的数学模型,并进一步对该系统的局部动态特性进行了讨论。理论分析表明这种新型的全数字锁相环具有很宽的锁相范围,并且在不同被锁频点的局部范围内都具有相同的稳定形式,锁相跟踪达到稳定的时间与被锁信号的周期成正比。由于充分利用了鉴相脉冲宽度所包含的相位误差信息,同时又引入了积分控制,使锁相环的跟踪响应速度得到提高。仿真实验进一步验证了理论分析的结论。该文锁相环采用数字电路方式实现,其性能可以通过比例和积分控制参数进行调节,因而简化了设计过程,便于应用在电机调速系统、有源滤波器和静止无功补偿器等领域。

A new design method of a all digital phase-locked loop (DPLL)is presented. The new DPLL controller is realized by a proportional-integral method rather than by conventional loop filters. A mathematic model for the DPLL is built with the method of linear approximation, and the local dynamic characteristics are developed. It is indicated by the theoretic analysis that the new design has wide lock-in range and has same stability behavior in the neigbourhood of the locked frequency. Besides, the frequency tracking time of the DPLL is directly proportional to the period of the locked signal. Utilizing the phase error indicated by the pulse width of phase detector outputs and employing the integral control improve the capture speed. The results obtained from simulation experiments confirm the conclusions of the theoretic analysis. Since the DPLL can be realized by digital circuits and can be regulated through the proportional and integral parameters, it is easy to be designed and be used in the fields of speed governing system of motor, active power filter and static var compensator.