QDRⅡ+SRAM PHY模块的设计研究

Design and Research on the PHY Module of QDRⅡ+SRAM

存储器与控制器的接口模块在如今多倍速率存储器(DDR,QDR等)中作为存储体和控制器之间信号的中转站起着至关重要的作用,接口模块通过时序的校准和数据的串并转换保证了高速数据有效的传输.研究了应用于网络设备的四字突发72Mb×36bQDR(4倍速率)Ⅱ+SRAM存储器接口的读写时序,针对其与控制器的接口协议详细论述了一种接口模块电路的实现方案,在500Mhz频率下完成了逻辑设计与验证以及版图物理设计工作.采用的移相时钟和延时校准机制提高了高速存储系统数据采集的可靠性.在tt,ss,ff三种不同器件端角下的验证结果满足四字突发QDRⅡ+SRAM存储器接口电路的时序和功能要求.该设计基于ASIC设计流程,模块面积小,功耗低,能够作为IP方便地应用于大型片上系统(system on chip,SOC)设计中,具有可移植性.

The interface between memory and controller is playing an important role as the signal transfer station between memory and controller in today's multi data rate memory.The interface ensure the efficient transmission of high-speed data by timing alignment and serial to parallel conversion of data.In this paper,we study the read and write timing in the interface of four-word burst 72Mb×36b QDR(quadruple data rate)Ⅱ +SRAM memory,an implementation scheme is discussed in detail of the interface against it's interface protocols with the controller and completed the logic design,verification and physical design of the interface in the frequency.Phase-shifted clock and delay calibration mechanism are used to improve the system reliability of data acquisition in high-speed storage system.The verification results in three different corners of device:tt,ss,ff meeting the timing and functional requirements in the interface of four-word burst QDRⅡ+SRAM memory.This design is based ASIC design flow with small area and low power and can be applied to large-scale SOC design and is portability.