期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

交互状态机模型模拟矢量自动生成方法 被引量：1

Automatic Simulation Vector Generation Using Interacting FSM Model
下载PDF
导出
摘要 模拟矢量自动生成方法是加速数字系统设计验证进程的有效手段.提出了一种针对数字系统交互状态机的状态组合、自动生成状态组合覆盖测度和状态组合覆盖模拟矢量的算法.与将交互状态机作为整体处理或构建状态机乘积的方法相比,该算法生成的模拟覆盖率测度精确,覆盖路径无回路,有效地提高了模拟验证的精度和速度.实验结果表明,该算法能高效地节省内存空间,较好地解决了状态空间爆炸问题. Automatic simulation vector generation is an efficient method to accelerate digital system's design verification process. An algorithm that generates coverage metrics and simulation vectors for state-pair of interacting FSM is presented in this paper. Compared with FSM (finite state machines) product method and the method which treats the interacting FSM as a single FSM, this algorithm can generate accurate coverage metrics and the shortest simulation vectors. Experimental results show that this algorithm is efficient in memory usage and perfectly solves the state space exploration problem.
作者 李暾 郭阳 李思昆
机构地区 国防科学技术大学计算机学院
出处 《软件学报》 EI CSCD 北大核心 2003年第3期628-634,共7页 Journal of Software
基金 Supported by the National Natural Science Foundation of China under Grant No.69933030 (国家自然科学基金)
关键词 交互状态机模型 模拟矢量自动生成方法 数字系统 覆盖率测度 Algorithms Finite automata Mathematical models Vectors
分类号 TP271.82 [自动化与计算机技术—检测技术与自动化装置]
  • 相关文献

参考文献14

  • 1[1]Ho R, Yang C, Horowitz M, Dill D. Architecture validation for processors. In: Patterson DA, ed. Proceedings of the International Symposium on Computer Architecture. Santa Margerita Ligure: ACM Press, 1995. 404～413.
  • 2[2]Shen J, Abraham JA. An RTL abstraction technique for processor microarchitecture validation and test generation. Journal of Electronic Testing: Theory and Application, 1999,16(1,2):67～81.
  • 3[3]Moundanos D, Abraham JA, Hoskote YV. Abstraction techniques for validation coverage analysis and test generation. IEEE Transactions on Computers, 1998,47(1):2～13.
  • 4[4]Geist D, Farkas M, Landver A, Lichtenstein Y, Ur S, Wolfsthal Y. Coverage-Directed test generation using symbolic techniques. In: Srivas MK, Camilleri AJ, eds. Proceedings of the Conference on Formal Methods in Computer-Aided Design. Palo Alto, CA: Springer-Verlag, 1996. 143～158.
  • 5[5]Aziz A, Kukula J, Shiple T. Hybrid verification using saturated simulation. In: Irwin MJ, ed. Proceedings of the 35th Design Automation Conference. San Francisco, CA: ACM Press, 1998. 615～618.
  • 6[6]Ho P-H, Shiple T, Harer K, Kukula JH, Damiano R, Bertacco VM, Taylor J, Long J. Smart simulation using collaborative formal and simulation engines. In: Proceedings of the International Conference on Computer Aided Design. San Jose, CA: IEEE Press, 2000. 120～126.
  • 7[7]Biere A, Cimatti A, Clarke E, Fujita M, Zhu Y. Symbolic model checking using SAT procedures instead of BDDs. In: Irwin MJ, ed. Proceedings of the 36th Design Automation Conference. New Orleans, LA: ACM Press, 1999. 317～320.
  • 8[8]Bryant RE. Graph-Based algorithms for Boolean function manipulation. IEEE Transactions on Computers, 1986,35(8):677～691.
  • 9[9]Liu CNJ, Yen C-C, Jou J-Y. Automatic functional vector generation using the interacting FSM model. In: Proceedings of the International Symposium on Quality Electronic Design. San Jose, CA: ACM Press, 2001. 372～377.
  • 10[10]Narayan A, Jain J, Fujita M, Sangiovanni-Vincentelli AL. Partitioned-ROBDDs--a compact, canonical and efficiently manipulable representation for Boolean functions. In: Rutenbar RA, Otten RHJM, eds. Proceedings of the International Conference on Computer Aided Design. San Jose, CA: ACM and IEEE Computer Society, 1996. 547～554.

同被引文献11

  • 1Daniel Diaz, Philippe Codognet. The GNU prolog system and its implementation. In: Proceedings of the ACM symposium on Applied Computing, Como, Italy, 2000, 728～732
  • 2Cheng K., Krishnakumar A.S.. Automatic generation of functional vectors using extended finite state machine model. ACM Transactions on Design Automation of Electronic Systems, 1996, 1(1): 57～79
  • 3Ferrandi F., Sciuto D., Fin A., Fummi F.. An application of genetic algorithms and BDDs to functional testing. In: Proceedings of IEEE International Conference on Computer Design, Austin, Texas, 2000, 48～58
  • 4Ganai M.K., Aziz A., Kuehlmann A.. Enhancing simulation with BDDs and ATPG. In: Proceedings of the 36th Design Automation Conference, New Orleans, US, 1999, 385～390
  • 5Ghosh I., Fujita M.. Automatic test pattern generation for functional RTL circuits using Assignment Decision Diagrams. In: Proceedings of the 37th Design Automation Conference, Los Angeles, US, 2000, 43～48
  • 6Farzan Fallah, Srinivas Devadas, Kurt Keutzer. Functional vector generation for HDL models using linear programming and Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(8): 994～1002
  • 7Venuri R., Kalyanaraman R.. Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Transactions on Very Large Scale Integration Systems, 1995, 3(2): 201～214
  • 8Pauli C., Nivet M.L., Santucci J.S.. Use of constraint solving in order to generate test vectors for behavioral validation. In: Proceedings of IEEE International High-Level Validation and Test Workshop, Berkeley, US, 2000, 15～20
  • 9Zeng Zhi-Hong, Maciej Ciesielski, Bruno Rouzeyre. Functional test generation using constraint logic programming. In: Proceedings of IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip, Montpellier, France, 2001, 133～138
  • 10Ferrandi F., Rendine F., Sciuto F.. Functional verification for System C descriptions using constraint solving. In: Proceedings of the Design, Automation, and Test in Europe, Paris, France, 2002, 744～751

引证文献1

软件学报
2003年 第3期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部