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基于神经网络的多核功耗预测策略 被引量:1

Neural Network Based Power Prediction Strategy for Multi-core Architecture
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摘要 多/众核处理器是计算机发展的趋势。在多/众核处理器的设计过程中,如何从庞大的设计空间中找出满足条件的设计结构,成为了关键和难点。为了解决传统软件模拟技术开销大、效率低等问题,提出了基于神经网络的模型来预测多核处理器的性能和功耗,建立了BP与RBF两种神经网络预测模型,利用SESC模拟器进行CPI与POWER模拟,并比较分析了两种预测模型的预测精度和可靠性。模拟结果表明,采用神经网络预测模型平均误差控制在1.6%~6.6%,较传统的软件模拟等方法,能更有效地节省时间、提高效率,其中,RBF神经网络预测模型具有更好的预测精度。 Multi/many-core processor is a trend of computer development.In the design process of multi-core processor,how to find the design structure from a large design space to meet the conditions has become a critical and challenging task.In order to solve the high overhead and low efficiency problem of traditional software simulation technology,this paper proposed a model based on neural network to predict the performance and power of multi-core processors,established two kinds of BP and RBF neural network prediction models,used SESC simulator to simulate CPI and power,and compared and analyzed the prediction accuracy and reality of two kinds of prediction models.Simulation results show that the neural network prediction model average error is 1.6%~6.6%in control.Compared to general software simulation method,it can also save time and improve efficiency.More importantly,RBF neural network prediction model has better prediction accuracy.
出处 《计算机科学》 CSCD 北大核心 2014年第S1期47-51,共5页 Computer Science
基金 国家自然科学基金(61303029) 留学回国人员科研启动基金([2012]1707) 中央高校基本科研业务费专项资金(2013-IV-054)资助
关键词 多核体系结构 机器学习 SESC模拟 预测模型 Multi-core architecture,Machine learning,SESC simulation,Prediction model
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  • 1张福新,章隆兵,胡伟武.基于SimpleScalar的龙芯CPU模拟器Sim-Godson[J].计算机学报,2007,30(1):68-73. 被引量:25
  • 2高翔,张福新,汤彦,章隆兵,胡伟武,唐志敏.基于龙芯CPU的多核全系统模拟器SimOS-Goodson[J].软件学报,2007,18(4):1047-1055. 被引量:16
  • 3Joseph P, Vaswani K, Thazhuthzveetil M J. Constructing and use of linear regression models for processor performance analysis // Proceeding of 12th International Symposium on High Performance Computer Architecture. Austin, Texas, 2006:99-108.
  • 4Dubach C, Jones T, O'Boyle M. Microarchitectural design space exploration using an architecture-centric approach // 40th IEEE/ACM International Symposium on Microachitecture. Chicago, Illinois, 2007:262-271.
  • 5Eeekhout L, Nussbaum S, Smith J, et al. Statistical simulation: adding efficiency to the computer designer's toolbox. IEEE Micro, 2003, 23(5): 26-38.
  • 6KleinOsowski A J, Lilja D J. MinneSPEC: a new SPEC benchmark workload for simulation-based computer architecture research. IEEE Computer Architectural Letters, 2002, 1(1): 7-10.
  • 7Sherwood T, Perehnan E, Hamerly G, et al. Automatically characterizing large scale program behavior// Proceeding of 10th International Conference on Architectural Support for Programming Languages and Operating Systems. San Jose, California, 2002:45-57.
  • 8Wunderlich R, Wenisch T, Falsafi B, et al. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling // Proceeding of 30th International Symposium on Computer Architecture. San Diego, 2003: 84-95.
  • 9Liu Wei, Huang M. EXPERT: expedited simulation exploiting program behavior repetition// Proceeding of 18th International Corfference on Supercomputing. Saint-Malo, France, 2004 : 126-135.
  • 10Gribal S, Mouchard G, Cohen A, et al. DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time. ACM SIGMETRICS Performance Evaluation Review, 2003, 31(1) : 1-12.

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