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SOC测试数据的编码压缩技术 被引量:4

System-on-a-Chip Test-Data Coding Compression Technology
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摘要 文章介绍了一种基于测试向量集的压缩/解压缩方法,目的在于弥补SOC测试中,测试设备存储容量不足的问题,分析了三种不同的编码方案,并从压缩率和解码电路的规模对它们作了比较,得出了使用Golomb编码来进行测试向量压缩/解压缩是简单而又行之有效的方法的结论。文章还给出了一个有效的最小海明距离排序算法,大大的提高了测试数据的压缩率。 We present a test-data compression/decompression scheme which is used to reduce the required memory of ATE.We analyze three kinds of encoding scheme,then make a com parison of them on the compression ratio and the complexity of the decoder,and draw a conclusion that Golomb encoding is an efficient and practicable compression/compression method.Fi nally,we present an efficient hamming distance ordering algorithm,which is proved to improve the compress gain especially.
出处 《微电子学与计算机》 CSCD 北大核心 2003年第2期44-47,共4页 Microelectronics & Computer
基金 国家自然科学基金重点项目(90207002) 北京市重点科技项目(H020120120130)
关键词 测试 编码压缩技术 SOC 哈夫曼编码 游程编码 Golomb编码 最小海明距离排序 系统集成技术 集成电路 SOC,Huffman code,Run-Length code,Golomb code,Minimum Hamming distance reordering
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参考文献5

  • 1[1]Y Zorian, E J Marinissern and S Dey. Testing embeddedcore based system chips. Proc. International Test Conference, 1998: 130~143.
  • 2[2]V D Agrawal and Chakraborty. High-performance circuit testing using slow-speed testers. in Proc. International Test Conference, 1995: 302~310.
  • 3[3]S W Golomb. Run-Length Encoding. IEEE Transactions on Information Theory, 1966,IT-12: 399~401.
  • 4[4]A Jas, J Ghosh-Dastidar and N A Touba. Scan vector compression/decompression using statistical coding. in Proc.IEEE VLSI Test Symp., May 1998:418~423.
  • 5[5]A Chandra, K Chakrabarty. System-on-a-Chip Test-Data Compression and Decompression Architectures Based on Golomb Codes. IEEE Transactions on Computer-aided design of Integrated circuits and systems, March 2001,20(3).

同被引文献24

  • 1韩银和,李晓维.测试数据压缩和测试功耗协同优化技术[J].计算机辅助设计与图形学学报,2005,17(6):1307-1311. 被引量:15
  • 2白玉媛,杨士元,王红.数字电路自动测试生成实用化软件[J].计算机应用研究,2006,23(1):174-176. 被引量:4
  • 3于文忠,牛道恒,杨士元.时序电路测试向量的压缩[J].微计算机信息,2006(07S):172-174. 被引量:5
  • 4Quasem M S, Gupta S. Designing reeonfigurable multiple scan ehains for systems-on-chip[C] //Proceedings of the 22nd IEEE VLSI Test Symposium, Napa Valley, 2004:365-371.
  • 5Han Y H, Hu Y, Li X W, etal. Wrapper scan chains design for rapid and low power testing of embedded cores [J]. IEICE Transactions on Information and Systems, 2005, E88-D(9): 2126-2134.
  • 6Niermann T, Patel J H. HITEC: a test generation package for sequential circuits [C] //Proceedings of European Conference on Design Automation, Amsterdam, 1991:214- 218.
  • 7Shintani M, Ohara T, Ichihara H, et al. A Huffman-based coding with efficient test application[C]//Proceedings of IEEE Asia and South Pacific Design Automation Conference, Shanghai, 2005:75-78.
  • 8Michael L Bushnell,Vishwani D Agawal.超大规模集成电路测试一数字、存储器和混合信号系统.北京:电子工业出版社,2005.8
  • 9Karim Arabi,Bozena Kaminska.Testing analog and mixedsignal integrated circuits using oscillation-test method IEEE Trans.on computer_aided design of integrated circuits and systems,1997,16(7):745~753
  • 10A Chandra,K Chakrabarty.System-on-a-chip test-data compression and decompression architectures based on golomb codes.IEEE Trans.Computer-Aided Design,2001,20(3):355~368

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