2Brann G Nobl A. A Universal Technique for Fast and Flexible Instruction-set Architecture Simulation [J]. IEEE Transactions on Computer-Aided Design of Integrated CircuitS and Systems, 2004,23 ( 12 ) : 1625 -1639.
3Leupers R. Compiler De sign Issues for Embedded Processors [ J]. IEEE Design and Test of Computers,2002,19(4) :51-58.
4C. Mills, S. C. Ahah, J. Fowler. Compiled instruction set simulation [ J ]. Software-Practice Exper, 1991, 21 ( 8 ) : 877 - 889.