摘要
介绍了一种应用于ARM处理器的增强DSP功能乘加单元。为了减小乘加指令的周期数,采用了两个并行16×16位乘加单元构成的单指令多数据(SIMD)结构,可以通过适当的配置支持16到32位的各种乘加运算以及16位的复数乘法。理论分析表明,这种乘加单元与传统的单指令单数据(SISD)结构相比在周期数上有明显的减小。尤其对于16位乘加及16位复数乘法,其所需周期数分别只有ARM1022E的1/4和1/3。0.35mm的标准单元库实现表明该乘加单元可以工作在120MHz,使得其非常适合数字信号处理的应用。
In this paper, a DSP-enhanced MAC unit with SIMD architecture for ARMmicroprocessor is proposed. By using two parallel 16-by-16 MACs, the proposed architecture canachieve great cycle reduction in multiplication of various lengths compared with conventional SISD(Single Instruction Single Data) architecture used in ARM. Especially for 16-bit MAC and 16-bitcomplex multiplication, the cycles needed are only 1/4 and 1/3 of ARM1022E. 0.35mm standard cellapplication shows that the MAC can run at 120MHz. These features make the MAC unit very suit-able for DSP applications.
出处
《半导体技术》
CAS
CSCD
北大核心
2003年第4期61-64,共4页
Semiconductor Technology
