面向星载应用的图像压缩专用芯片研制

Image Compression ASIC for Satellite Remote Sensing Application

以高数据吞吐量和低系统结构复杂性为优化目标 ,根据图像传感器输出特点 ,综合应用双缓存、数据流驱动、并行处理与流水线设计、同步电路设计等多项关键技术 ,设计了具有数据处理速度和超大规模集成电路VLSI(VeryLargeScaleIntegrated)结构复杂性最佳匹配的空间域重采样压缩算法VLSI结构 ,该结构的压缩性能仅与图像宽度相关 ,与图像传感器输出时序无关 ,既可以采用外部时钟 ,又可使用与图像传感器相同的时钟源 ,在这 2种情况下 ,都能够保证在无限长时间内 ,在连续工作状态下 ,每个时钟周期实时处理一个图像数据 .实践证明 ,基于该VLSI结构的压缩专用芯片 ,处理速度快 ,功耗低 。

A VLSI architecture for the algorithm of combining re sampling with multi mode adaptive quantization was proposed. With low hardware complexity and fast computation rate, the architecture can deal with huge amount of data and match the requirement of VLSI architectures in regularity, modularity, locality. Based on the architecture, ASIC for real time compression application for high resolution satellite remote sensing imagery was designed and manufactured using FPGA(Field Programmable Gate Arrays). An outstanding feature of the ASIC is that it can process one pixel during each clock cycle. At the clock frequency of 36?MHz, a peak processing speed as high as 288Mbits/s of the image compression ASIC can be reached, with a power consumption lower than 1?W.