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实现Viterbi译码器幸存路径存储及译码输出的一种新方法 被引量:3

Novel Approach to the Survivor Memory and Decode Out in Viterbi Decoder FPGA Designing
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摘要 提出了一种幸存路径存储及输出的新方法———SMDO法,该方法与传统的寄存器交换法和回索法相比具有存储量小、译码延迟短的特点,并且极适合利用FPGA内置的EAB块实现。 In this paper a novel approach to the survivor memory and decoding out put outSMDO method was presented. Compared with the traditional techniquesregister exchange(RE) and trace back(TB), this method needs smaller memory and shorter decoding delay. It's very suitable for FPGA implementation.
出处 《应用科技》 CAS 2003年第3期25-26,32,共3页 Applied Science and Technology
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  • 1侯伯亨 顾新.VHDL硬件描述语言与数字逻辑电路设计[M].西安:西安电子科技大学出版社,1999..
  • 2王新梅 肖国镇.纠错码原理与方法[M].西安:西安电子科技大学出版社,2001..

共引文献185

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  • 1王新梅,肖国镇.纠错码原理与方法[M].西安:西安电子科技大学出版社,2001.445.
  • 2HURWITZ M, BRAUN R. A Generalized Design Tech- nique for Traeeback Survivor Memory Management in Vit- erbi Decoders [ C]. Communications and Signal Process- ing, 1997. 63-68.
  • 3LOU Hui- ling. Implementing the Viterbi algorithm[ J ]. IEEE Signal Processing Magazine, 1995, 12:42 -52.
  • 4HEKSTRA A P. An alternative to metric rescaling in Vit- erbi decoders [ J ]. IEEE Transactions Communications, 1989, 37(11) : 1220-1222.
  • 5王新梅;肖国镇.纠错码——原理与方法[M]西安:西安电子科技大学出版社,2001.
  • 6FORNEY J G D. The Viterbi Algorithm[J].PROCEEDINGS OF THE IEEE,1973,(03):268-278.
  • 7周炯架;庞沁华.通信原理[M]北京:北京邮电大学出版社,2002.
  • 8FETTWEIS G,MEYR H. Parallel Viterbi algorithm implementation:Breaking the ACS-bottleneck[J].IEEE Transactions on Communications,1989,(08):785-790.
  • 9RADER C. Memory management in a Viterbi decoder[J].IEEE Transactions on Communications,1981,(09):1399-1401.
  • 10FEYGIN G,GULAK P. Architectural tradeoffs for survivor sequence memory management in Viterbi decoders[J].IEEE Transactions on Communications,1993,(03):425-429.

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