一种能够提高驱动能力和ESD保护能力的亚微米CMOS输出晶体管的新设计方法

New Layout Design for Submicron CMOS Output Transistors to Improve Driving Capability and ESD Robustness

本文给出了一种新的输出驱动器的设计方法 ,利用这种方法可以有效地减少 CMOS输出驱动器的面积 ,同时提高驱动能力和 ESD可靠性。输出驱动器是由许多电路单元组成的 ,电路单元有正方形、六边形和八边形三种形状。利用这种新的设计风格制成的输出晶体管结构更加对称 ,在 ESD过程中触发更一致。理论计算和实验证明 ,在非硅化物 CMOS工艺中 ,在小的设计面积内 ,利用新的设计方法研制成的 CMOS输出缓冲器的输出驱动能力更高 ,ESD保护能力更强。有许多电路单元组成的输出晶体管和传统的指状设计相比 ,栅电阻更低 。

New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability id proposed.The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes.The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events.With theoretical calculation and experimental verification, both higher output driving/sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout.