一种应用VHDL语言设计有限状态机控制器的方法

A Kind of Method to Design the Finite State Machine Controller with VHDL Language

本文对利用 VHDL语言设置有限状态机控制器的过程进行系统的论述。通过对控制器控制对象的时序分析 ,抽象出控制器的行为描述 ,并划分控制器的状态。在此基础上 ,针对ADC0 80 9模数转换器的控制器进行设计 ,并通过了系统仿真和逻辑分析仪测试。

This article systemically states the process of establishing the Finite State Machine.By analyzing the timing of the controlled objection,the controller's behavioral statement can been abstract and its state can been carved up too.Based on it,design the ADC0809's controller.The project has passed the systemic simulation and the test of the logic analyzer.So a kind of method to design the finite state machine controller with VHDL language is proposed.