高速大容量多通道数据采集系统设计

Design of High-Speed,Large-Scale and Multi-Channel Data Acquisition System

根据某型号通信实验系统中数据采集单元的设计要求 ,提出了一种高速、大容量、多通道数据采集系统的设计方案。该方案以同步动态存储器 ( Synchronous dynamic random access memory,SDRAM)组成的计算机内存条为存储介质 ,以现场可编程门阵列 ( Field programmable gate array,FPGA)为数字逻辑控制的核心 ,并通过硬件描述语言 ( VHSIC hardware description language,VHDL)编程实现了控制 SDRAM所需的接口电路 ,从而使硬件电路软件化 ,降低了硬件成本。本文重点介绍了该采集系统的硬件设计原理和软件设计框架。

According to the design demand of the data acquisition unit in a communication test system, a new design scheme for the high-speed, large-scale and multi-channel data acquisition system is proposed. It stores the input data in memory bank composed of synchronous dynamic random access memory (SDRAM), uses field programmable gate array (FPGA)as the core of logical control, and implements the interface circuits by hardware description language (VHDL)programming. The basic design principles for hardware and the program frame for software are analyzed. The data acquisition system is used in practice.