JPEC2000率失真斜率计算的浮点操作及其VLSI结构研究

VLSI Architecture For Floating-Point Computation of JPEG2000 Rate-Distortion

在采用 JPEG2000算法的图像压缩芯片结构研究中,我们发现编码(EBCOT)部分的计算结构是相当复杂的。其中率失真计算结构是否合理,直接关系到编码算法的效率。本文着重阐述了完成率失真浮点计算所必需的硬件结构;提出了新型的专用于率失真计算的除法算法及其结构;在保证计算精度和速度的前提下,最大限度地降低了计算结构的复杂度。本论文提出的计算结构已通过 RTL 级源代码和综合布线后门级仿真,并经过 Xilinx FPGA 测试线路板上运行验证。为确保 JEPG2000图像编码芯片的最终成功流片解决了一个关键问题。

In the research of a reasonable ASIC computation architecture for the JPEG2000 encoder (EBCOT),whether the structure for rate-distortion is fast,precise and economy enough,is one of the key points to realize an efficient JPEG2000 encoder hardware.This article focuses on the hard- ware structure of floating-point computation for the rate-distortion,and presents an innovative struc- ture for the pertinent divider so that redundant resource is reduced furthest and the equivalent speed needed still remains.All the strategies in this paper were verified through both post layout simulation with Verilog and hardwired logic running on a test PCB of Xilinx FPGA,thus assure the success of the design.