一个高效的嵌入式浮点FFT处理器的实现

Implementation of a Highly Efficient Embedded Floating FFT Processor

FFT是数字信号处理中的一种非常重要的算法。本文构造了一个适于嵌入式应用的基16FFT处理器局部流水结构,同时设计实现了一个高效的基4蝶形运算模块。我们的研究应用了局部流水和反馈的思想,使基16FFT蝶形运算模块得以由两个基4/基2蝶形模块组成的反馈流水电路实现,在简化结构的同时提高了处理速度。基4蝶形模块中运算模块的利用率达到100％,而且比传统的基四蝶形模块节省60％以上的资源。

FFT is a very important algorithm in digital signal processing. This paper presents a locally pipeline architecture for radix-16 FFT processor which suits embedded applications, at the same time a high efficiency version of radix-4 butterfly module is designed in it. We apply the method of local pipeline and feedback in our research, in this way a feedback pipeline circuit using two radix-4/2 butterfly modules implements the radix-16 FFT butterfly module. It not only improves the processing speed but also simplify module structure. In this paper, the processing module service efficiency is up to 100%. Comparing with the traditional radix-4 butterfly modules, our research saves resource more than 60 percent.