CDMA并行匹配滤波器的CPLD设计

Implementing CDMA Parallel Matched Filter in CPLD Devices

根据FLEX10K系列CPLD器件中查找表结构的特点和节省器件资源原则,采用折叠滤波技术和复杂可编程逻辑器件设计了CDMA并行匹配滤波器.输入数据宽度为8位,输出数据宽度为16位,过采样率为16,通过EDA- 型开发系统将设计硬件编程到FLEX10K芯片中,并在MAX+Plus 开发环境中进行了仿真分析.

According to the LUT construction of programmable logic device (PLD) in FLEX10K series and the saving resources principle, we designed a code division multiple access (CDMA) parallel match filter by using the folded filter and complex programmable logic device (CPLD). The input data width is 8 bits, the output data width is 16 bits, and the chip rate is 16. Using the EDAⅣ development system, we realized hardware programming on the FLEX10K chip, and completed simulate analysis in the MAX+Plus Ⅱ.