摘要
在采用定长 CPU周期设计的 RISC微处理器解释指令时 ,为了保证 CPU周期的完整性而降低了 CPU的效率。通过异步信号将节拍电位寄存器复位的不定长 CPU周期设计的 RISC微处理器 ,在运行相同的机器语言程序时 ,明显快于采用定长 CPU周期的微处理器。
For the integrality of the CPU period, the CPU efficiency of the fixed-length CPU period microprocessor has accordingly to be lowered in the process of instruction's explanation.This paper introduces the designing approach of a RISC microprocessor of non fixed-length CPU period.This new type of microprocessor is able to function at much faster rate in running the same kind of programme.A summary of the testing results of the new type microprocessor's performance is also provided.
出处
《桂林电子工业学院学报》
2003年第2期59-62,共4页
Journal of Guilin Institute of Electronic Technology
基金
桂林电子工业学院科学基金资助项目 ( Z2 0 0 10 8)
