用FPGA实现53位数据流的编解码和纠错

Implementing Coding and Decoding and Error Correcting of 53-bit Data Flow with FPGA

以工程为背景 ,介绍了基于 ISE平台 VHDL语言设计采用 FPGA实现 5 3位数据流的编解码和错误码的纠检错的方法 ,此方法采用并行处理 ,处理能力强 ,复杂度低 。

With the engineering background,the method of realizing 53 digit data flow coding,encoding and error code correction are introduced based on ISE platform VHDL language design.The method utilizes parallel processing,having a super processing ability,low complexity and a super engineering application potention.