一种具有动态带宽校正功能的锁相环

A Phase-Locked Loop with Dynamic Bandwidth Calibration

提出了一种锁相环的动态带宽校正方法。通过监测压控振荡器的频率增益、反馈调节电荷泵电流,对锁相环的带宽进行补偿,保证锁相环的闭环带宽始终大于信号速率。采用该方法,能够在兼顾设计复杂度和低噪声的情况下,获得最小的锁相环闭环带宽裕度,降低功耗。基于SMIC 0.18μm 1P4M CMOS工艺,实现了一个2.4GHz的频率调制发射机芯片。发射机采用单点输入结构,可对锁相环进行直接调制,整个芯片面积仅为1.54mm2。测试结果表明,该方法可以动态校正因VCO频率增益变化引起的锁相环带宽偏差,实现了数据的稳定传输。

A dynamic bandwidth calibration method for phase locked-loop(PLL)was presented.During the process of calibration,frequency gain of VCO was measured firstly,and then charge pump current was adjusted to compensate the PLL’s bandwidth to ensure the PLL’s closed-loop bandwidth larger than the transmission data rate.With the proposed structure and method,a minimum closed-loop bandwidth margin and the merits of low noise and moderate complicity were achieved.A 2.4 GHz frequency modulation transmitter chip was realized in SMIC 0.18μm 1 P4 M CMOS technology.A single-point modulation structure was used in this transmitter to modulate directly the PLL.The whole chip area was only 1.54 mm2.Measurement results showed that the PLL bandwidth deviation caused by VCO’s frequency gain changing could be calibrated dynamically with the proposed method,and to avoid data missing in communications.