一种基于扩展栅的改进的双通道OPTVLD p-LDMOS

An Improved Dual-Path OPTVLD p-LDMOS Using Extended Gate

提出了一种具有超低比导通电阻的新型优化横向变掺杂双通道p-LDMOS。与传统结构相比,该结构在器件表面增加了一个自驱动的扩展栅。该扩展栅不仅显著提高了导通时空穴的导电能力,还改善了阻断时器件表面的电场分布。因此,新结构的击穿电压(VB)与比导通电阻(Ron,sp)之间的折中关系得到显著改善。仿真结果显示,击穿电压为328V的新结构的Ron,sp为75mΩ·cm^2,仅为同条件下传统结构的48.8%,并且可与同工艺下制作的323Vn-LDMOS的Ron,sp(84mΩ·cm^2)相媲美。这为智能功率集成电路提供了更多更好的选择。

A novel dual-path optimum variation lateral doping p-LDMOS with enhanced current conductive ability was proposed.Compared with the conventional structure,the proposed structure featured an addition of self-driven extended gate at the device’s surface.This extended gate not only significantly enhanced the hole-conductive capability when the device was turned on,but also improved the distribution of the surface electric field when the device was turned off.As a result,the relationship between breakdown voltage(VB)and specific on-resistance(Ron,sp)was improved.Simulation results indicated that the proposed structure with a VBof about 328 Vexhibited a Ron,spof 75 mΩ·cm^2,which was only 48.8% of the conventional structure with the same VB,and even approximated to the Ron,spof an n-LDMOS with a VB of about 323 Vunder the same manufacturing process.It provided more and better options for smart power ICs.