基于比较器亚稳态抑制技术的8位320 MS/s SAR ADC

An 8 bit 320 MS/s SAR ADC with Comparator Meta-Stability Immunity Technique

提出一种比较器亚稳态抑制技术,并将其应用于一个8位320 MS/s的逐次逼近型模数转换器(SAR ADC)。该技术抑制了比较器在高速工作情况下可能出现的亚稳态现象,从而降低了比较器出现错误结果的概率。同时,提出一种转换时间复用技术,使ADC能在转换与采样模式之间快速切换。与传统技术相比,随着工艺角、电源电压和温度(PVT)的变化,ADC的采样时间会被最大化。基于65 nm CMOS工艺,设计了一种8位320 MS/s SAR ADC。芯片测试结果表明,在1 V电源电压下,功耗为1 mW,信号噪声失真比(SNDR)>43 dB,无杂散动态范围(SFDR)>53.3 dB。SAR ADC核的芯片面积为0.021 mm^2,在Nyquist采样率下,优值为29 fJ/step。

An 8-bit 320-MS/s successive approximation register(SAR)analog-to-digital converter(ADC)with a comparator meta-stability immunity technique was presented.Dynamic comparator with meta-stability immunity technique was provided to suppress the wrong decision behavior at high conversion rate.Moreover,a conversion time recycling technique was utilized to increase the sampling time of SAR ADC.With the proposed conversion time recycling technique,a new sampling phase would begin after the ending of last conversion as soon as possible.Thereby,with the variations of PVT,the sampling time was maximized compared with previous techniques.To demonstrate the proposed techniques,a design example of SAR ADC was fabricated in a 65 nm CMOS technology,consuming 1 mW at a 1 V power supply.It achieved an SNDR>43 dB and an SFDR>53.3 dB at 320 MS/s.The ADC core occupied an active area of only 0.021 mm^2 and the corresponding figure-of-merit(FoM)was 29 fJ/step with Nyquist rate.