摘要
基于40 nm CMOS工艺,设计了一种前馈架构的3阶1位量化离散时间Σ-Δ调制器。该调制器的信号带宽为100 kHz,过采样比为128。为了适应低电压环境,输入端开关采用栅压自举结构以提升采样信号的线性度,运算放大器采用两级结构以增加输出摆幅。为了降低系统功耗,比较器采用动态结构实现。仿真结果表明,在1.2 V电源电压下,该调制器的最高信噪比为88.1 dB,功耗为1.5 mW。
A 3 rd-order single-bit discrete-timeΣ-Δmodulator with feed forward architecture was designed in a 40-nm CMOS technology.The signal bandwidth was 100 kHz and the oversampling ratio(OSR)was 128.In order to meet low voltage requirements,a bootstrapped switch was used at the input to improve the linearity of sampled signals,and two-stage amplifiers were utilized to increase the output swings.Besides,the dynamic comparator was employed to reduce the system power.The simulation results showed that the proposed modulator achieved 88.1 dB maximum signal-to-noise ratio(SNR)under 1.2 V supply,and the power consumption was 1.5 mW.
作者
陈笑
王志功
黎飞
CHEN Xiao;WANG Zhigong;LI Fei(Institute of RF-&OE-ICs,Southeast University,Nanjing210096,P.R.China)
出处
《微电子学》
CAS
北大核心
2019年第3期331-335,共5页
Microelectronics
基金
国家自然科学基金资助项目(6504000177)
关键词
Σ-Δ调制器
前馈架构
栅压自举开关
两级运算放大器
Σ-Δmodulator
feed forward architecture
bootstrapped switch
two-stage operational amplifier