摘要
设计了一种具有上电启动功能的差分环形压控振荡器(VCO),该电路可作为时钟产生模块应用于SoC中的高速锁相环(PLL)。该VCO采用全差分延迟结构,可更好地抑制来自电源的共模噪声。增加了使控制电压变化可控的上电启动电路,便于控制PLL中环路开启次序,缩短PLL锁定时间,为延迟单元提供适当的初始偏置和起振条件。基于GF 28 nm标准CMOS工艺进行电路设计、仿真和版图设计。仿真结果表明,该VCO具有良好的起振可靠性和稳定性,输出频率调谐范围为0.65~3.9 GHz。在1 V电源电压、1.625 GHz中心频率时,相位噪声为-80.44 dBc/Hz@1 MHz,功耗为6.6 mW。应用该VCO的PLL的测试结果表明,锁定时间为1.6μs,频率调谐范围和锁定时间均优于对比文献。
A differential ring voltage controlled oscillator(VCO)with power-on start function was designed,which was used as a clock generation module for the applications of high speed phase locked loops(PLL)in SoC.A fully differential delay structure was used to suppress the common mode noise from the power supply.To ensure the control voltage variation of the VCO was controllable,a power-on starting circuit was incorporated,so as to control the opening sequences of the loop,to shorten the lock time of the PLL,and to provide an appropriate initial offset and starting conditions for delay unit.Circuit design,simulation and layout design were based on GF 28 nm standard CMOS process.The simulation results showed that the proposed VCO had an excellent start-up reliability and stability,and the tuning range of output frequency was 0.65~3.9 GHz.The phase noise was-80.44 dBc/Hz@1 MHz,and the power consumption was 6.6 mW under 1.0 V power supply and 1.625 GHz center frequency.The PLL with the proposed VCO had a lock time of 1.6μs.The frequency tuning range and lock time of the VCO were superior to the referred literatures.
作者
刘雨婷
刘兴辉
孙嘉斌
李威
王绩伟
LIU Yuting;LIU Xinghui;SUN Jiabin;LI Wei;WANG Jiwei(School of Physics,Liaoning Univ.,Shenyang110036,P.R.China;Beijing Chongxin Commun.Technol.Co.,Ltd.,Beijing100041,P.R.China;Institute of Computing Technol.,Chinese Academy of Sci.,Beijing100190,P.R.China)
出处
《微电子学》
CAS
北大核心
2019年第4期471-476,共6页
Microelectronics
基金
国家自然科学基金资助项目(11574124)
辽宁省教育厅研究生教育教学改革项目(辽教函[2017]24号)