一种65 nm CMOS低功耗加固SRAM单元

A Low Power Radiation Hardened SRAM Cell in 65 nm CMOS Technology

提出了12管低功耗SRAM加固单元。基于堆叠结构,大幅度降低电路的泄漏电流,有效降低了电路功耗。基于两个稳定结构,可以有效容忍单粒子翻转引起的软错误。Hspice仿真结果表明,与相关加固结构相比,该结构的功耗平均下降31.09%,HSNM平均上升19.91%,RSNM平均上升97.34%,WSNM平均上升15.37%,全工作状态下均具有较高的静态噪声容限,表现出优秀的稳定性能。虽然面积开销平均增加了9.56%,但是,读时间平均下降14.27%,写时间平均下降18.40%,能够满足高速电子设备的需求。

A 12T low power SRAM radiation hardened cell was proposed.Based on the stack structure,the leakage current of the circuit was greatly reduced,and the power consumption of the circuit was effectively reduced.Based on two stable structures,soft errors caused by the single event upset could be effectively tolerated.The comprehensive Hspice simulation results showed that,compared with the related hardened structures,the power consumption of the proposed structure was reduced by 31.09%on average,the HSNM was increased by 19.91%on average,the RSNM was increased by 97.34%on average,and the WSNM was increased by 15.37%on average.The Static Noise Margin(SNM)was high in all conditions with an excellent stability performance.Although the area overhead was increased by an average of 9.56%,the average reading time was decreased by 14.27%,and the write time was decreased by an average of 18.40%,which could meet the needs of high speed electronic equipments.