基于可编程逻辑器件的二维卷积器IP设计

Development of 2-D Convolvers IP Core Based on FPGA

提出了一种图像处理用二维卷积器的 IP设计 .该卷积器的设计基于将一帧完整的图像分解为多个相互重叠的垂直窄带 ,而将每个垂直带视为一幅完整图像进行处理 ,因此大大减少了系统所用移位寄存器的数目 ,但系统的性能下降较少 .用 Verilog HDL语言描述了整个系统的设计 ,并在 Xilinx公司的 ISE4 .1集成开发环境下进行了仿真和逻辑综合 ,给出了实现的结果 .

An IP design of 2-d convolver for image processing was introduced in this paper. The design is based on dividing the entire image into several vertical bands and treating every band as narrow, but complete images. A substantial economy in the number of shift registers required could be achieved by this way. The development was implemented under Xilinx ISE4.1, in which Verilog HDL program of the IP module was captured, and the result of simulation and synthesis was given.