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基于关键面积的冗余集成电路成品率分析 被引量:5

Analysis of Redundant Integrated Circuit Yield Based on Critical Area
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摘要 利用关键面积的思想分析了冗余电路的成品率 ,并给出了其计算模型 .实例模拟表明 ,与传统的成品率分析方法相比 ,该模型预测 IC成品率具有更高的精度 . Yield of the redundant circuit is analyzed with IC critical area and the computational model of this redundant circuit is given.The simulation results of an example show that the precision is higher using the presented model to predict IC yield than using the traditional yield model.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2003年第5期544-549,共6页 半导体学报(英文版)
基金 国家科技攻关和陕西省教育厅科研计划 ( No.0 2 JK194)资助项目~~
关键词 关键面积 冗余集成电路 成品率 故障 缺陷 critical area fault yield defect
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参考文献4

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同被引文献41

  • 1王俊平,郝跃,张卓奎,任春丽,李康,方建平.椭圆缺陷轮廓的成品率估计[J].西安电子科技大学学报,2006,33(3):433-437. 被引量:2
  • 2Campbell S A. The science and engineering of microelectronic fabrication. Bejing:Publishing House of Electronics Industry, 2003
  • 3Milor L S. Yield modeling based on in-line scanner defect sizing and circuit's critical area. IEEE Trans Semicond Manuf, 1999,12(1):26
  • 4Hess C,Weiland L H. Issues on the size and outline of killer defects and their influence on yield modeling. IEEE/SEMI ASMC 96 Proceedings, 1996:423
  • 5Jiang Xiaohong, Hao Yue. Equivalent circular defect model of real defect outlines in the IC manufacturing process. IEEE Trans Semicond Manuf,1998,11(3) :432
  • 6Stoneking D. Improving the manufacturability of electronic designs. IEEE Spectrum, 1999,36(6) : 70.
  • 7Keramat M, Kielbasa R. Generalized centers of gravity algorithm for yield optimization of integrated circuits. Proceedings of the 1998 IEEE International Symposium on Circuit and System, 1998(6):334.
  • 8Director S, Hachtel G, Vidigal L. Computationally efficient yield estimation procedures based on simplicial approximation. IEEE Trans Circuits Syst, 1978,25(3):121.
  • 9Hastie T,Tibshirani R, Friedman J. The elements of statistical learning: Data mining, inference, and prediction. New York: Springer, 2001.
  • 10Avant, Star-Hspice Manual, 2001 : 576.

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