用FPGA实现高频时钟的分频和多路输出

The Realization of Division and Multichannel Output of High-Frequency Clock Using the FPGA

FPGA(现场可编程逻辑门阵列 )内部集成了四个全数字片内延时锁定环电路 (Delay -LockedLoop ,缩写为DLL) ,利用它能够实现对芯片输入时钟的零延时输出和时钟倍频 ,分频以及镜像操作等多种控制功能。本文就是用DLL的功能来实现对 6

FPGA provides four fully digital dedicated on-chip Delay-Locked Loop(DLL) circuits, Which provides zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system level design.