摘要
针对用于PCIE2.0物理层的8b/10b编码器及其扩展的16b/20b编码器,设计了一种新的实现方式.将8b/10b编码分为5b/6b编码和3b/4b编码两个子模块,根据PCIE2.0协议中规定的编码表采用极性分组和卡诺图化简的方式得到子模块逻辑表达式并组合实现8b/10b编码.然后分析了由其扩展的16b/20b编码器中3种不同流水线级数的实现方式,使用Synopsys的Design Compiler工具在SMIC55 nm工艺下进行综合,在250 M时钟频率下的组合逻辑资源面积仅为223μm^2,并根据综合结果分析了流水线级数对编码器性能的影响.
An Implementation of 8 b/10 b encoder and its extended 16 b/20 b encoder for PCIE2.0 physical layer is designed.The 8 b/10 b coding is divided into 5 b/6 b sub-coding and 3 b/4 b sub-coding.Based on the code table specified in PCIE2.0 protocol,using disparity group and Karnaugh map to get and simplify the 8 b/10 b logic expression.Then the three different implementation of 16 b/20 b encoder using pipeline was discussed,and systhesised under SMIC 55 nm process using Sysnopsys’s Design Compiler tool,the combinational logic resource area at 250 MHz is only 223μm^2,the effect of pipeline stage on the encoder performance is analyzed according to the systhesis result.
作者
蔡万楼
赵建中
吕英杰
Cai Wanlou;Zhao Jianzhong;LüYingjie(College of Electronic Information and Optical Engineering,Nankai University,Tianjin 300457,China;Serdes Department,Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100020,China)
出处
《南开大学学报（自然科学版）》
CAS
CSCD
北大核心
2019年第2期34-38,共5页
Acta Scientiarum Naturalium Universitatis Nankaiensis
