摘要
实现随机等效采样系统的关键技术是短时间测量和波形重构技术。传统系统中使用的时间测量方法里,精度较高且节省成本的是游标卡尺法,但由于其难以产生两个频率极其接近的时钟从而增加了系统的实现难度。该系统的实现中,使用了状态法——通过调用PLL构成内插时钟并捕获有效边沿对应的状态来测量时间,该方法兼顾了测量精度和硬件成本;同时,该系统也简化了波形重构用到的随机排序算法,进一步降低了系统实现的复杂度,最后在FPGA开发板上验证了此方法的正确性与可行性。
Key technologies to realize random equivalent sampling system area short-time measurement and waveform reconstruction.Measurements of time used in conventional system with high precision and cost savings is the Vernier caliper method,but because of it's difficult to produce two clock who's frequency are close that increasing its difficulty of the implementation. The implementation of the system using the method of state by calling the PLL constitute interpolation clock and capturing the corresponding effective edges' states to measure time,the method considers both the accuracy of measurement and the hardware cost; At the same time,the system simplifies the random sort algorithm using in waveform reconstruction,further reduce the complexity of system implementation,and finally validate the correctness and feasibility on the FPGA development board.
出处
《南阳理工学院学报》
2016年第2期5-8,共4页
Journal of Nanyang Institute of Technology
关键词
随机等效采样
短时间测量
随机排序算法
FPGA
random equivalent sampling
short time measurement
random sort algorithm
FPGA
