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DSP芯片中浮点加法器LOD电路的设计

A Design of LOD for DSP Floating-Point Adder
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摘要 DSP芯片中浮点加法器的速度制约着整个芯片的工作速度,浮点加法器中LOD电路的速度又是浮点加法器工作速度的瓶颈。因此,我们可以通过对LOD电路的改进,来提高整个DSP芯片的工作性能。我们从LOD的组成结构和逻辑两个方面进行设计,实现了一种快速、高效的LOD电路。它针对处理的数据格式为TMS320C3X扩展精度浮点数据格式。 The speed of floating-point adder is important factor for DSP performance.The speed of LOD is key factor for float-ing-point adder performance.So,in order to improve the speed of DSP,we can use the way that improve the speed of LOD.Through the structure and logical designing,we get a high-speed and effective LOD circuit,which applied in floating-point adder.The TMS320C3X Extended-Precision Floating-Point Format is used by this LOD design.
出处 《微电子学与计算机》 CSCD 北大核心 2003年第4期60-62,65,共4页 Microelectronics & Computer
关键词 浮点加法器 LOD电路 设计 DSP芯片 数字信号处理器 运算速度 DSP,Floating-point,LOD,Normalize
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参考文献5

  • 1Peter M. Scidel University of Saarland Computer Science Department 66041 Saarbruecken, Germany; Guy Even Tel-Aviv University Electrical Engineering Department 69978 Tel-Aviv,Israel; An IEEE Floating-Point Adder Design Optimized For Speed; VLSI in Computers&Processors, Austin,Texas. Oct. 1998:142-149.
  • 2R V K,Pillai D Al-Khalifi and A J Al-Kbalili. A Low Power Approach to Floating Point Adder Design. Concordia University, Montreal. Natural Sciences and Engineering Research Council (NSERC) of Canada.
  • 3A Beaumont-Smith, N Burgsec, S Lefrere,C C Lim ChiPTec.Department of Electrical and Electronic Engineering. The University of Adelaide. Reduced Ltency IEEE Floating-Point Standard Adder Architectures.
  • 4Javier D. Bruguera Dept. of Electronic and Computer Eng.University of Santiago de Compostela,Spain; Tomas Lang Dept. Electrical and Computer Eng. University of California at Irvine;Loading-One Prediction Scheme for Iatency Improvement in Single Dataphth Floating-point Adders;CICYT(Spain) contract TIC96-1125-c03.
  • 5TMS320C3X.User's Guide,1997.

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