通用乘法器IP核可测性设计研究

Research on the design for the testability of the general multiplier

为了改善所研制的运动视觉系统芯片(SOC)中乘法器IP的可测性,采用基于内建自测试的方法,在外围增加改进的线性反馈移位寄存器和多输入特征寄存器,对乘法器IP内部进行测试.所实现的测试结构对乘法器的内部结构和运算速度影响很小,而且测试结构所占的比例也很小.仿真实验的结果表明,这种乘法器IP的可测性设计方法对提高测试覆盖率非常有效.

Multipliers are widely used in DSP and computer vision processors. To improve the testability of this model, a DFT method, BIST, is used, which implements an improved LFSR as a test pattern generator, and an MISR as a signature analyzer to the multiplier. This BIST structure has a little influence on the inner multiplier structure and its speed. The test results show that it obtains a high fault coverage and it can be used in other similar circuits.