一种面向总线的容错式多处理器或多计算机网络结构

A CLASS OF FAULT-TOLERANT BUS-ORIENTED ARCHITECTURE FOR MULTIPROCESSOR AND MULTICOMPUTER SYSTEMS

本文提出一种面向总线的容错式多处理器或多计算机网络结构,它由处理器/计算机节点和总线节点构成.文中用两类节点的二分图表示所提出的网络结构,并讨论了其与一般图表示方法问的关系.对网络结构的连接矩阵、两类节点的容错能力、通信直径等概念进行了定义和讨论.从均衡总线负载能力和处理器通讯接口数考虑,二者处处相等且两类节点数相等的结构最有前途.文中还提出了两类节点线度均为3、且两类节点数相等的二种均匀多总线网络结构.

This paper proposes a uniform multibus architecture, which consists of two types of nodes: the processor or computer node and the bus node. The architecture is represented by a bipartite graph and its relation with a general graph is also discussed. The concepts related to the connectivity, the capacity of fault-tolerance and the diameter of communication for the two types of nodes are defined and discussed. Furthermore, two kinds of uniform multibus architectures with degree 3 and same node number for two types of nodes are also proposed in this paper.