32位浮点阵列乘法器的设计及算法比较

Design of a 32-Bit Floating-Point Array Multiplier and a Comparison of Algorithms

讨论了乘法器用于补码运算的几种算法。通过比较,发现改进型Booth算法是较为理想的算法。该算法在不考虑乘数和被乘数符号的情况下,都可以用统一的步骤来完成乘法运算,而且无需对乘积作任何修正,这极大地提高了乘法器的运算速度。结合改进型Booth算法,设计了一个高性能32位浮点阵列乘法器,它能在单个时钟周期内完成一次24位整数乘或32位浮点乘。该乘法器适于VLSI实现,已被应用于DSP芯片设计之中。

Algorithms for two's complement multiplication are discussed It has been found that Modified Booth Algorithm is an ideal algorithm, which can accomplish multiplication without considering signs of multiplier and multiplicand, eliminating the need for modifying the product, so that the operation speed of the multiplier is greatly improved The algorithm has been implemented in a 32bit floatingpoint array multiplier, which performs singlecycle multiplications on 24bit integer or 32bit floatingpoint values The multiplier is suitable for VLSI implementation and has been used in DSP chip design