期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

16×16位高速低功耗并行乘法器的实现 被引量：1

A High-speed and Low-power 16×16-bit Parallel Multiplier
下载PDF
导出
摘要 　基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。 A highspeed and lowpower 16×16bit parallel multiplier in very large scale integration based on 06μm doublewell CMOS process is described in the paper In order to achieve lowpower operation, the multiplier was designed utilizing passtransistor logic circuits New circuit implementations for Modified Booth Encoder and 42 compressor circuitries have been proposed and simulated At a supply voltage of 25 V, multiplication time of the multiplier for the worst case is 718 ns and the average power dissipation is 945 mW at a frequency of 100 MHz
作者 徐锋 邵丙铣
机构地区 复旦大学国家微电子材料与元器件微分析中心
出处 《微电子学》 CAS CSCD 北大核心 2003年第1期56-59,共4页 Microelectronics
关键词 BOOTH编码 并行乘法器 VLSI 传输管逻辑 低功耗 Booth encoder Parallel multiplier VLSI Pass-transistor logic
分类号 TP332.22 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献9

  • 1Inoue A, Ohe R, Kashi S,et al. A 4. 1 ns compact 54 × 54-b multiplier utilizing sign select booth encoders[A] Proc Int Solid-State Circuits Conf [C]. 1997.416-417.
  • 2Wallace C S. A suggestion for a fast multiplier [J].IEEE Trans Electron Comput, 1964; 13(2): 14-17.
  • 3Kwentus A Y, Hung H T, Willson A N, et al. An architecture for high-performance/small-area multipliers for use in digital filtering applications [J]. IEEE J Sol Sta Circ, 1994; 29(2): 117-121.
  • 4Macsorley O L. High-speed arithmetic in binary computers [A]. Proc IRE [C]. 1994.67-91.
  • 5Abu-Khater I S, Bellaouar A, Elmasry M I. Circuit techniques for CMOS low-power high-performance multipliers [J]. IEEE J Sol Sta Circ, 1996; 31(10):1535-1546.
  • 6Law C F, Rofail S S, Yeo K S. A low-power 16×16-b parallel multiplier utilizing pass-transistor logic [J].IEEE J Sol Sta Circ, 1999;34 (10):1395-1399.
  • 7Mori J. A 10-ns 54×54-bit parallel structured full array multiplier with 0. 5-μm CMOS technology [J].IEEE J Sol Sta Circ, 1991; 26(4): 600-606.
  • 8Ohkubo N, Suuki M, Shinbo T, et al. A 4.4 nsCMOS 54× 54-b multiplier using pass-transistor multiplier [J].IEEE J Sol Sta Circ, 1995; 30(3): 251-257.
  • 9Wang J-M, Fang S-C, Feng W-S. New efficient designs for XOR and XNOR functions on the transistor level [J]. IEEE J Sol Sta Circ, 1994; 29(7) :780-786.

同被引文献12

  • 1侯华敏,杨虹.高性能乘加单元的设计[J].微电子学,2005,35(5):509-512. 被引量：3
  • 2崔晓平.基于修正BOOTH编码的32×32位乘法器[J].电子测量技术,2007,30(1):82-85. 被引量：2
  • 3田心宇,张小林,姚英.一种可重构的高速流水线乘法器[J].电路与系统学报,2007,12(3):33-36. 被引量：2
  • 4LEE R B,SMITH M D.Media processing:a new design target[J].IEEE Micro,1996,16(4):6-9.
  • 5MENARD D,CASSEAU E,KHAN S,et al.Reconfigurable operator based multimedia embedded processor[C] // 5th Int Workshop Reconfigurable Computing:Architectures,Tools and Applications.Berlin,Germany.2009:39-49.
  • 6IWATA E,OLUKUTUN K.Exploiting coarse-grain parallism in the MPEG-2 algorithm[Z].Media Processing Laboratories,Sony Corporation.1998:1-13.
  • 7WEY C-L,LI J-F.Design of reconfigurable array multipliers and multiplier-accumulators[C] // The 2004 IEEE Conf Circ and Syst.Tainan,Taiwan,China.2004:37-40.
  • 8HONG Sanjin,MUN J-H.Design and implementation of a high-speed matrix multiplier based on word-width decomposition[J].IEEE Trans VLSI Syst,2006,14 (4):380-392.
  • 9MACSORLEY O L.High-speed arithmetic in binary computers[J].Proc IRE,1961,49(1):67-91.
  • 10WALLACE C S.A suggestion for a fast multiplier[J].IEEE Trans Elec Comp,1964,13(1):14-17.

引证文献1

二级引证文献1

微电子学
2003年 第1期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部