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一种改进的能量回收逻辑电路 被引量:1

An Improved Energy Recovery Logic Circuit
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摘要  文章分析了能量回收电路的功耗组成,指出非绝热损失是能量回收电路的主要功耗能量来源,提出了一种改进的能量回收逻辑电路IERL。IERL电路增加了额外的回收路径,能够显著降低电路的非绝热损失,HSPICE模拟结果表明,IERL电路具有很好的低功耗性能。同时,给出了IERL电路的复杂逻辑门设计与级联方式,用0.8μmDPDM工艺实现了2位IERL全加器电路和两相正弦功率时钟电路。 The power consumption in energy recovery circuit is analyzed in this paper Results show that the nonadiabatic loss is the main source of power consumption Based on this fact, an improved energy recovery logic (IERL) structure is proposed IERL has additional recovery paths, and by improving the recovery percentage through the additional recovery path, it can reduce the nonadiabatic loss HSPICE simulation demonstrates that IERL circuit can greatly improve the low power performance Complex gate design and cascading of IERL circuits are also considered, which are easy to implement A 2bit full adder of IERL and a twophase sinusoidal power clock generator circuit were fabricated with 08 μm DPDM CMOS technology
出处 《微电子学》 CAS CSCD 北大核心 2003年第2期140-143,147,共5页 Microelectronics
基金 国家自然科学基金资助课题(59995550-1) 清华大学985关键研究基金资助课题。
关键词 低功耗 能量回收 CMOS电路 非绝热损失 IERL Low power Energy recovery CMOS circuit Non-adiabatic loss
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参考文献6

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同被引文献5

  • 1ALEX G D, JOHN S D. Adiaabatic dynamic logic [J].IEEE journal of solid-state circuits, 1995,30(3): 311-315.
  • 2YONG M,DENG K J.An efficient charge recovery logic circuit[J]. IEEE journal of solid-state circuits, 1996,31(4), 514-522.
  • 3LAU K T ,LIU E IAPDL-based low power adiabatic programmable logic array[J].Microelectronics Journal, 2002;31:235-238.
  • 4NG K W, NG KA, LAU K T.Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structure [J]. Microelectronics Journal, 1999(30):851-854.
  • 5NG K W,LAU K T.ECRL-based low power flip-flop design[J]. Microelectronics Journal, 2000(31 ): 365-370.

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