摘要
提出了深亚微米下系统级芯片层次式版图设计的方法,并用该方法设计了HDTV信道解码芯片8VSB的版图。实例设计结果表明,该方法在节约面积、加速时序收敛方面效果明显,大大缩短了芯片设计周期。
A method for hierarchical layout design of SOC in verydeep submicron (VDSM) technology is presented in the paper, which is used to design the layout of an ATSC compliant cable channel signal decoder IC for HDTV It can be concluded from the design example that, using this method, chip area can be reduced, and the timing convergence could be significantly accelerated, and what's more, the design cycle is greatly shortened
出处
《微电子学》
CAS
CSCD
北大核心
2003年第2期151-153,共3页
Microelectronics
基金
2001年高等学校骨干教师资助计划项目
