16×16位带符号/无符号基于RTL级实现的可综合的高速乘法器

A 16×16 Bit Signed/Unsigned Synthesizable High-Speed Multiplier in High Level RTL Code

提出了一种综合使用改进后的Booth编码算法、Wallace树形结构、先行进位加法器 ,利用HDL进行RTL级的高速运算的乘法器的设计。它可以方便地应用于不同的工艺库。逻辑设计与工艺设计是互不相关的。设计的代码经过仿真和综合后表明 ,采用TSMC 0 .18μm的工艺库在温度为 2 5℃ ,电源电压为 1.8V的情况下 ,最小延迟 (criticalpath)为 3.5ns,在时钟频率为 2 0 0MHz时 ,芯片面积为 2 6 2 77.0 95 7μm2 ,平均功耗为 7.12 3mW。

This paper presents a new multiplier, which makes use of modified signed/unsigned Booth encoder, Wallace Tree and carry look-ahead adder. The multiplier is designed with HDL in high level RTL code, so it is suitable to any process. Logic design techniques are indepen-dent of process technology. Using the TSMC 0.18 μm process, simulation and synthesis of the RTL code show that critical path of multiplication is 3.5 ns at a supply voltage of 1.8 V and a temperature of 25 ℃ , and the area is 26277.0957μm 2, the average power dissipation is 7.123 mW at a frequency of 200 MHz.