芯片尺度封装中焊线的应力分析研究

Stress analysis on gold wire of chip scale package

芯片尺度封装(CSP)技术是近年来发展最为迅速的微电子封装新技术。通过对WB-CSP器件中金线(GoldWire)所受应力的有限元模拟,发现金线所受应力与塑封材料的膨胀系数、焊点大小、金线粗细、金线拱起高度等因素有关。结果表明:由于热失配引起的金线应力最大处位于金线根部位置,SEQVmax=625.202MPa,在通常情况下,这个部位在所承受的应力作用下产生的形变最大,最有可能发生断裂,引起器件的失效。模拟结果与实际失效情况相一致。此外,发现:当环氧树脂塑封料热膨胀系数为1.0×10-5/oC时,金线最大等效应力出现最小值,SEQVmax=113.723MPa,约为原来的1/6;随着金线半径减小、焊点增大,金线所受应力也将减小。模拟结果对于WB-CSP封装设计具有一定的指导意义。

Chip scale package (CSP) is a new microelectronic packaging technology rapidly deve- loped in recent years. The failure of the gold wires of CSP is analyzed by the Finite Element Analysis Software-ANSYS . The stress on gold wire is found to be subject to the CTE (Coefficient of Temperature Expansion) of mold compound, ball bond radius, wire radius and wire high. The maximum stress (SEQVmax=625.202MPa), due to thermal mismatch, is located on the root of wire. The results from both experiment and simulation show that the failure of package usually occurred on this location. It is found that the minimum stress of the wire (SEQVmax=113.723MPa), which is about 1/6 of the formal when the CTE of mold equals to 1.0×10-5/oC, and that the stress of the wire decreases with the decrease of the wire radius and the increase of the ball bond radius.