VHDL及高层综合

VHDL and High-level Synthesis

本文简单介绍了VHDL硬件描述语言及其特色 ,并就高层次综合、高层次仿真及验证等技术的主要功能和特点 ,作了较为详细的描述。对目前国外两家公司的高层综合工具做了简要介绍。最后 ,提出了一些待研究解决的问题。

This paper introduces VHDL and its feature briefly.At meantime,it describes high level synthesis and high level simulation technology in detail.The author also mentions a certain synthesis of an oversea company.In the end,some problems are brought forward to be solved.