VHDL语言对微程序设计思想的描述及模拟的应用

The application of VHDL language in describing and simulating the microprogram design idea

提出了以VHDL语言为手段,针对微程序设计思想进行描述和模拟,从而达到在制造硬件电路之前就可以验证设计思想的正确性.

This Paper proposeded the application of VHDL Language in describing and simulating the microporgram design idea,thereby we can test and verify the correctness of microprogram design idea before manufacturing hardware circuit.