数字电路平行故障模拟方法的研究与实现

The Research and Implementation of Parallel Fault Simulation for Digital Circuits

本文用平行的方法实现了对数字电路的故障模拟。对于组合电路,通过引入敏感输入的概念,大大提高了算法的实现效率。对于时序电路,通过将触发器展开成基本门的形式,在门级描述的基础上实现了故障模拟。本文最后给出了对十个电路例子(ISCAS Benchmark Cicuits)的模拟结果。这种故障模拟方法的研究对提高测试产生的效率有一定的帮助。

This paper implements a fault simulation system for digital circuits. The concept of sensitizing -in put is used to enhance the efficiency of combinational circuits. For sequential circuits, we expand the flip-flops to basic gates. As a result.the esperimental results of 10 ISCAS Benchmark Circuits are given.