ULSI中的铜互连线RC延迟

RC Delay Technology of Copper Interconnection in USLI

随着ULSI向深亚微米特征尺寸发展,互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高,同时考虑到电迁移和功率损耗,人们开始寻找新的互连材料;低电阻率的铜互连材料和低介电常数介质的结合可以有效地改善互连线的性能。主要讨论了互连延迟的重要性以及改善和计算延迟的方法。

The Information Revolution and enabling era of silicon ultralarge - scale integration (ULSI) have spawned an ever - increasing level of functional integration on - chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance - limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L) delay as well as electromigration and power dissipation concerns have stimulated the introduction of low - permittivity dielectrics to provide performance and reliability enhancement. In this paper, the importance of researching RC delay, the methods of improving and calculating RC delay are discussed.