一个基于软件流水技术的VLIW体系结构

SOFTWARE PIPELINING BASED VLIW ARCHITECTURE

本文叙述一个正在开发的VLIW多处理单元单片机,这个机器的体系结构基于URPR软件流水技术,采用了流水寄存器堆来减少体间相关距离,因此,细粒度并行性可得到充分开发,从而提高了循环体重叠程度,使得优化后的循环体的长度可大大缩短.模拟实验结果表明,这个体系结构在优化编译器的配合下可达到很高的性能。

This paper introduces a VLIW architecture which is now under development. Based on URPR software pipelining approach, the architecture integrates nine PEs with same structure on a single chip. In addition, pipeline register file is used to reduce the inter-body dependent distance and to enhance the overlapping of the adjacent loop iterations, furthermore to shorten the length of the optimized loop body. Pipeline register file also increases the bandwidth between PEs. Therefore, the fine-grained parallelism can be fully exploited. Simulation results indicate that the architecture could reach high performance with the aid of an optimizing compiler.