一种低功耗低噪声相关双取样电路的研究

Low-Power Low-Noise Correlated Double Sampling Circuit for CMOS Image Sensor

为了尽量在前级消除CMOS图像传感器读出电路中的主要噪声源,本文提出一种低功耗低噪声的相关双取样电路,开关晶体管采用PMOS晶体管代替传统的NMOS晶体管,避免了NMOS管的阈值损失,有效地降低功耗而不减小信号摆幅,降低了1/f噪声。与传统CDS电路相比较,所提出的CDS电路的输出采用对称列选通开关和源跟随晶体管,减少了两个电流源晶体管和一个偏置电源,有效地降低了功耗;同时,现有工艺能制造出性能匹配很好的对称晶体管,有效地消除器件本身由于阈值偏差带来的固定平面噪声。模拟结果表明,在电源电压为3.3V的情况下,像素单元响应动态范围(输出幅值接近电源电压) 较宽,像素单元及CDS正常工作时消耗的能量是1.73μW。

f noise, KTC noise and fixed pattern noise (FPN) are the main noise sources of the readout circuit of the CMOS image sensor. In order to eliminate them as earlier as possible as to improve the signal-noise-ratio, a low-power low-noise correlated double sampling (CDS) circuit is proposed for CMOS image sensors. In this circuit, PMOSFETs are used as the switch transistors to decrease the power dissipation without lowering the signal amplitude and to reduce the 1/f noise. Unlike conventional CDS, symmetrical transistors of both column switches and the source-follower are chosen for the output stage of the proposed CDS. In this way, two-column-load transistors and one bias power supply can be saved as to reduce the power dissipation effectively. By means of present art, well-matched and symmetric transistors can be implemented to eliminate the FPN noise, which arise from the mismatched threshold voltage of the transistors in the circuit. Simulation results show that the power dissipation of the pixel cell and the proposed CDS is as low as 1.73μW at the power supply voltage 3.3V, while the dynamic output amplitude approaches the power supply voltage .