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低成本基板倒装焊底充胶分层裂缝扩展研究 被引量:1

Underfill Delamination of Flip Chip on Low-Cost Board
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摘要 采用MIL STD 883C热循环疲劳加载标准 ,通过电学检测方法测定了B型和D型两种倒装焊封装焊点寿命。并使用无损声学C SAM高频超声显微镜技术观测这两种倒装焊封装在焊点有无断裂两种情况时芯片 /底充胶界面的分层和扩展 ,计算得到分层裂缝扩展速率。在有限元模拟中采用粘塑性和时间相关模量描述了SnPb焊点和底充胶的力学行为。使用裂缝尖端附近小矩形路径J积分方法作为断裂力学参量得到不同情况下的界面分层裂缝顶端附近的能量释放率。 Following thermal cycling loading standard, MIL STD 883C, the life of two types of test chips (type B and D) are determined with electrical measure. And the delamination propagation behavior at the interface between chip and underfill is investigated and the crack propagation rates are measured by using C SAM inspection for those samples. The material properties of SnPb eutectic solder used in simulation are modeled by the Anand viscoplastic material model. Meanwhile for underfill U8437 3, not only the Young's modulus but also the coefficients of thermal expansion are temperature dependent. Moreover, in the related finite element simulations, the strain energy release rates near crack tip under different conditions are calculated by the J integral in a small rectangular path near the crack tip. Then, the Paris helf empirical equation, which can be used as a reliability design base of flip chip package, is determined through the crack propagation rates measured and the energy release rates simulated.
出处 《应用力学学报》 CAS CSCD 北大核心 2003年第2期22-26,共5页 Chinese Journal of Applied Mechanics
基金 国家自然科学基金重点项目 批准号 :1983 40 70 上海市科技发展基金项目 编号 :99ZD14 0 5 5
关键词 倒装焊 底充胶 分层裂缝扩展 电学检测 断裂力学 有限元模拟 半导体 封装技术 flip chip, underfill, interfacial delamination and crack propagation, finite element simulation, fracture mechanics.
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