摘要
介绍了应用VHDL技术设计嵌入式数字锁相环的方法 ,给出了系统仿真结果 ,并用可编程逻辑器件FPGA予以实现。该锁相环能够实现正交锁定或反相锁定 ,并具有控制灵活、锁定频率高和系统稳定性好等特点。
The design of embedded digital phase-locked loops with VHDL is introduced , and simulation result is given. The DPLL is implemented with FPGA . It can realize quadrature or reversed phaselocked. The DPLL is more agile in control , higher in locking frequency and better in stability.
出处
《计算机仿真》
CSCD
2003年第6期93-95,42,共4页
Computer Simulation
