用FPGA实现较大规模的CAM

Using FPGA to Implement Medium Size CAM

介绍了一种利用Xilinx公司FPGA中分布式RAM来实现 10 2 4× 2 8bitCAM的方法。该方法有效利用了FPGA中的资源 ,使得在FPGA中构造较大规模CAM成为可能。使用该方法构造的CAM具有灵活方便、扩展性强、工作时钟频率高、写入需 1个时钟周期、查询需 18个时钟周期等特性。针对该CAM查询周期较长的缺点 ,在ATM应用中 ,提出一种对ATMheader进行预处理来提高CAM利用率的方法 ,使该CAM实现 5 0 0万次 /s查表操作。

The method for designing a flexible, high performance, efficient medium size CAM by using the distributed RAM in FPGA offered by Xilinx is introduced. The size of this kind of CAM is up to 1 024 ×28 bit which can meet many ATM applications. CAM implemented in this way uses a single clock cycle to write and 18 clock cycles to find a match. In ATM applications, a way to enhance the efficiency of CAM is advanced to make it possible to execute match operation 5 million times per second.