超高速数据采集时钟分系统的设计与实现

Design and Implementation of Clock System of High Speed Data Acquisition

为了提高数据采集系统采集数据的分辨率和抗干扰能力,要求时钟分系统能够产生具有高精度、高稳定度、低抖动的采样时钟.介绍了一种基于程控频率合成器的时钟电路的设计思想、性能特点、工作原理和硬件电路设计,讨论了采样时钟抖动对量化误差的影响以及时钟电路的阻抗匹配和电磁兼容性.

In order to improve the distinguished rate and the anti-jamming ability of high speed of data acquisition system, clock circuit must produce sampling clock with high accuracy, high stabilization and low clock jitter. A clock system based on frequency synthesizer in high speed of data acquisition system is introduced. It includes design idea, character, working principle and hardware design of the clock circuit. The paper also discusses the problem of clock jitter, impedance matching, and electromagnetic compatibility in the system.